ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF522/524/526 and
ADSP-BF523/525/527 processors are listed in Table 10. In order
to maintain maximum function and reduce package size and
ball count, some balls have dual, multiplexed functions. In cases
where ball function is reconfigurable, the default state is shown
in plain text, while the alternate function is shown in italics.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate.
All I/O pins have their input buffers disabled with the exception
of the pins that need pull-ups or pull-downs, as noted in
Table 10.
It is strongly advised to use the available IBIS models to ensure
that a given board design meets overshoot/undershoot and sig-
nal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D.
The termination resistors should be placed near the processor to
reduce transients and improve signal integrity. The resistance
value, typically 33 Ω or 47 Ω, should be chosen to match the
average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure to
verify overshoot/undershoot and signal integrity specifications
on actual hardware.
Table 10. Signal Descriptions
Signal Name
EBIU
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
AMS3–0
ARDY
AOE
ARE
AWE
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Type Function
O Address Bus
I/O Data Bus
O Byte Enables/Data Mask
O Bank Select
I Hardware Ready Control
O Output Enable
O Read Enable
O Write Enable
O SDRAM Row Address Strobe
O SDRAM Column Address Strobe
O SDRAM Write Enable
O SDRAM Clock Enable
O SDRAM Clock Output
O SDRAM A10 Signal
O SDRAM Bank Select
Driver
Type1
A
A
A
A
A
A
A
A
A
A
A
B
A
A
Rev. PrG | Page 22 of 80 | February 2009
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