ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
ADSP-BF523/525/527 Clock Related Operating Conditions
Table 15 describes the core clock timing requirements for the
ADSP-BF523/525/527 processors. Take care in selecting MSEL,
SSEL, and CSEL ratios so as not to exceed the maximum core
clock and system clock (see Table 17). Table 16 describes phase-
locked loop operating conditions.
Table 15. Core Clock (CCLK) Requirements—ADSP-BF523/525/527 Processors—All Speed Grades1
Parameter
fCCLK
Core Clock Frequency (VDDINT =1.14 V minimum)2
fCCLK
Core Clock Frequency (VDDINT =1.093 V minimum)3
fCCLK
Core Clock Frequency (VDDINT = 0.95 V minimum)
1 See the Ordering Guide on Page 80.
2 Applies only to 600 MHz speed grades. See the Ordering Guide on Page 80.
3 Applies only to 533 MHz and 600 MHz speed grades. See the Ordering Guide on Page 80.
Internal Regulator Setting
1.20 V
1.15 V
1.0 V
Max
600
533
400
Unit
MHz
MHz
MHz
Table 16. Phase-Locked Loop Operating Conditions
Parameter
fVCO
Voltage Controlled Oscillator (VCO) Frequency
1 See the Ordering Guide on Page 80.
Minimum
50
Maximum
Unit
Speed Grade1
MHz
Table 17. ADSP-BF523/525/527 Processors Maximum SCLK Conditions
Parameter
VDDEXT/VDDMEM = 1.8 V
Nominal1
VDDEXT/VDDMEM = 2.5 V/3.3 V
Nominal
Unit
fSCLK
CLKOUT/SCLK Frequency (VDDINT ≥ 1.14 V)2
fSCLK
CLKOUT/SCLK Frequency (VDDINT < 1.14 V)2
100
1333
MHz
100
100
MHz
1 If either VDDEXT or VDDMEM are operating at 1.8V nominal, fSCLK is constrained to 100MHz.
2 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 34 on Page 44.
3 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 34 on Page 44.
Rev. PrG | Page 30 of 80 | February 2009
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