ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF526BBCZ-4AX

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE

register. Set this register prior to using the TWI port.

Table 11. TWI_DT Field Selections and VDDEXT/VBUSTWI

TWI_DT

000 (default)1

VDDEXT Nominal

3.3

VBUSTWI Minimum

2.97

VBUSTWI Nominal

3.3

VBUSTWI Maximum

3.63

001

1.8

1.7

1.8

1.98

010

2.5

2.97

3.3

3.63

011

1.8

2.97

3.3

3.63

100

3.3

4.5

5

5.5

101

1.8

2.25

2.5

2.75

110

2.5

2.25

2.5

2.75

111 (reserved)

–

–

–

–

1 Designs must comply with the VDDEXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.

ADSP-BF522/524/526 Clock Related Operating Conditions

Table 12 describes the core clock timing requirements for the

ADSP-BF522/524/526 processors. Take care in selecting MSEL,

SSEL, and CSEL ratios so as not to exceed the maximum core

clock and system clock (see Table 14). Table 13 describes phase-

locked loop operating conditions.

Table 12. Core Clock (CCLK) Requirements—ADSP-BF522/524/526 Processors—All Speed Grades1

Parameter

fCCLK

Core Clock Frequency (VDDINT =tbd2 V minimum)

fCCLK

Core Clock Frequency (VDDINT =tbd4 V minimum)

fCCLK

Core Clock Frequency (VDDINT = tbd5 V minimum)

fCCLK

Core Clock Frequency (VDDINT = tbd V minimum)

fCCLK

Core Clock Frequency (VDDINT = tbd V minimum)

1 See the Ordering Guide on Page 80.

2 Preliminary data indicates a value of 1.33 V.

3 Applies only to 400 MHz speed grade only. See the Ordering Guide on Page 80.

4 Preliminary data indicates a value of 1.235 V.

5 Preliminary data indicates a value of 1.14 V.

Max

4003

350

300

TBD

TBD

Unit

V

V

V

V

V

V

V

–

Unit

MHz

MHz

MHz

MHz

MHz

Table 13. Phase-Locked Loop Operating Conditions

Parameter

fVCO

Voltage Controlled Oscillator (VCO) Frequency

1 See the Ordering Guide on Page 80.

Minimum

50

Maximum

Unit

Speed Grade1

MHz

Table 14. ADSP-BF522/524/526 Processors Maximum SCLK Conditions

Parameter

fSCLK

CLKOUT/SCLK Frequency (VDDINT ≥ tbd V)1

VDDEXT/VDDMEM = 1.8 V/2.5 V/3.3 V Nominal

80

fSCLK

CLKOUT/SCLK Frequency (VDDINT < tbd V)

tbd

1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 34 on Page 44.

Unit

MHz

MHz

Rev. PrG | Page 28 of 80 | February 2009

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