STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

IX - EXTERNAL REGISTERS

These registers are located in shared memory. Initiate Block Address Register (IBAR) gives the Initiate

Block Address (IBA) in shared memory (see Register IBAR(34)H on Page 73).

‘Not used’ bits (Nu) are accessible by the microprocessor but the use of these bits by software is not

recommended.

IX.1 - Initialization Block in External Memory

Descriptor Address

Channel

Address

bit15

bit8

bit7

bit0

T

CH 0

R

IBA+00

IBA+02

IBA+04

IBA+06

Not used

TDA High

Transmit Descriptor Address (TDA Low)

Not used

RDA High

Receive Descriptor Address (RDA Low)

T

CH1

R

IBA+08

IBA+10

IBA+12

IBA+14

Not used

TDA High

Transmit Descriptor Address (TDA Low)

Not used

RDA High

Receive Descriptor Address (RDA Low)

CH 2

to

CH30

IBA+16

to

IBA+246

T

CH 31

R

IBA+248

IBA+250

IBA+252

IBA+254

Not used

TDA High

Transmit Descriptor Address (TDA Low)

Not used

RDA High

Receive Descriptor Address (RDA Low)

When Direct Memory Access Controller receives Start from one of 64 channels, it reads initialization block

immediately to know the first address of the first descriptor for this channel.

Bit 0 of Transmit Descriptor Address (TDA Low) and bit 0 of Receive Descriptor Address (RDA Low), are

at ZERO mandatory. This Least Significant Bit is not used by DMA Controller, The shared memory is

always a 16 bit memory for the DMA Controller.

N.B. If several descriptors are used to transmit one frame then before transmitting frame, DMA Controller

stores the address of the first Transmit Descriptor Address into this Initialization Block.

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