STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

IX - EXTERNAL REGISTERS (continued)

IX.3.2 - Bits written by the Rx DMAC only

CFT : Frame correctly transmitted

CFT = 1, the Frame has been correctly transmitted.

CFT = 0, the Frame has not been correctly transmitted.

ABT

UND

: Frame Transmitting Aborted

ABT = 1, the frame has been aborted by the microprocessor during the transmission.

ABT = 0, the microprocessor has not aborted the frame during the transmission.

: Underrun

UND = 1, the transmit FIFO has not been fed correctly during the transmission.

UND = 0, the transmit FIFO has been fed correctly during the transmission.

IX.3.3 - Transmit Buffer

Each transmit buffer is defined by its transmit descriptor.

The maximum size of the buffer is 2048 words (1 word=2 bytes)

15

0

TBA

First Word to Transmit

TBA + x ;

NBT is odd : x = NBT - 1

NBT is even : x = NBT - 2

Last Word to Transmit

IX.4 - Receive & Transmit HDLC Frame Interrupt

bit15

bit8 bit7

NS 0 Tx A4 A3 A2 A1 A0 0 0

bit 0

0 CFT/CFR BE/BF HALT EOQ RRLF/ERF

This word is located in the HDLC interrupt queue ; IQSR Register indicates the size of this HDLC interrupt

queue located in the external memory.

NS : New Status.

Before writing the features of event in the external memory the Interrupt Controller reads the

NS bit :

if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the status word of the frame

which has been transmitted or received.

if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).

When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new

status. This location becomes free for the Interrupt Controller.

Transmitter

Tx : Tx = 1, Transmitter

A4/0 : Tx HDLC Channel 0 to 31

RRLF : Ready to Repeat Last Frame

In consequenceof event suchas Abort Command HDLC, Controller is waiting Start or Continue.

EOQ : End of Queue

The Transmit DMA Controller (or the Receive DMA Controller) has encountered the current

Descriptor with EOQ at ”1”. DMA Controller is waiting ”Continue” from microprocessor.

HALT : The TransmitDMAController hasreceivedHALT from the microprocessor; it is waiting”Continue”

from microprocessor.

BE : Buffer Empty

If BINT bit of Transmit Descriptor is at ‘1’, the Transmit DMA Controller puts BE at ”1” when the

buffer has been emptied.

CFT : Correctly Frame Transmitted

A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is

at ‘1’. CFT is located in the last descriptor if several descriptors are used to define a frame.

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