Z8F041APJ020EG 查看數據表（PDF） - Zilog
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Z8F041APJ020EG Datasheet PDF : 282 Pages
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Z8 Encore! XP® F082A Series
Product Specification
115
Bit
[2]
TDRE
[1]
TXE
[0]
CTS
Description (Continued)
TDRE—Transmitter Data Register Empty
This bit indicates that the UART Transmit Data Register is empty and ready for additional data.
Writing to the UART Transmit Data Register resets this bit.
0 = Do not write to the UART Transmit Data Register.
1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted.
Transmitter Empty
This bit indicates that the Transmit Shift Register is empty and character transmission is finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS Signal
When this bit is read it returns the level of the CTS signal. This signal is active Low.
UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 66. UART Status 1 Register (U0STAT1)
Bit
7
6
5
4
3
2
1
0
Field
Reserved
NEWFRM MPRX
RESET
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R/W
R/W
R
R
Address
F44H
Bit
[7:2]
[1]
NEWFRM
[0]
MPRX
Description
Reserved
These bits are reserved and must be programmed to 000000.
New Frame
A status bit denoting the start of a new frame. Reading the UART Receive Data Register
resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
Multiprocessor Receive
Returns the value of the most recent multiprocessor bit received. Reading from the UART
Receive Data Register resets this bit to 0.
UART Transmit Data Register
Data bytes written to the UART Transmit Data (UxTXD) Register, shown in Table 67, are
shifted out on the TXDx pin. The Write-only UART Transmit Data Register shares a Reg-
ister File address with the read-only UART Receive Data Register.
PS022827-1212
PRELIMINARY
UART Control Register Definitions
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