Z8F041APJ020EG 查看數據表（PDF） - Zilog
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Z8F041APJ020EG Datasheet PDF : 282 Pages
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Z8 Encore! XP® F082A Series
Product Specification
118
The UART data rate is calculated using the following equation:
UART Baud Rate (bits/s) = -1---6-----S----yU---s--A-t--e-R--m--T-----CB----la-o---u-c--d-k----RF----ra--e--t-qe----u-D--e---in-v---ci-s--y-o---(-r-H---V--z--a-)--l-u----e-
For a given UART data rate, calculate the integer baud rate divisor value using the follow-
ing equation:
UART Baud Rate Divisor Value (BRG) = RoundS--1---y6--s----t-e---U-m---A---C-R---l-T-o---c-D--k---a--F-t--a-r--e--R-q---ua----et-e--n---c(--b-y---i-t-(-s-H--/-s-z--)-)-
The baud rate error relative to the acceptable baud rate is calculated using the following
equation:
UART Baud
Rate
Error (%)
=
100
-A----c---t-u----a---l---D----a---D-t-a---e--R-s---i-ar--e-t--e-d---–-D----D-a---te--a--s---iR-r--e-a--d--t-e--D-----a---t--a-----R----a---t--e--
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 72 provides information about the data rate errors for popular baud rates and com-
monly used crystal oscillator frequencies.
Table 72. UART Baud Rates
10.0 MHz System Clock
Acceptable BRG Divisor Actual Rate Error
Rate (kHz) (Decimal)
(kHz)
(%)
1250.0
N/A
N/A
N/A
625.0
1
625.0
0.00
250.0
3
208.33 –16.67
115.2
5
125.0
8.51
57.6
11
56.8
–1.36
38.4
16
39.1
1.73
19.2
33
18.9
0.16
9.60
65
9.62
0.16
4.80
130
4.81
0.16
2.40
260
2.40
–0.03
1.20
521
1.20
–0.03
0.60
1042
0.60
–0.03
0.30
2083
0.30
0.2
3.579545 MHz System Clock
5.5296 MHz System Clock
Acceptable BRG Divisor Actual Rate Error
Rate (kHz) (Decimal)
(kHz)
(%)
1250.0
N/A
N/A
N/A
625.0
N/A
N/A
N/A
250.0
1
345.6 38.24
115.2
3
115.2
0.00
57.6
6
57.6
0.00
38.4
9
38.4
0.00
19.2
18
19.2
0.00
9.60
36
9.60
0.00
4.80
72
4.80
0.00
2.40
144
2.40
0.00
1.20
288
1.20
0.00
0.60
576
0.60
0.00
0.30
1152
0.30
0.00
1.8432 MHz System Clock
PS022827-1212
PRELIMINARY
UART Control Register Definitions
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