Z8F041APJ020EG 查看數據表（PDF） - Zilog

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Z8F041APJ020EG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

116

Table 67. UART Transmit Data Register (U0TXD)

Bit

7

6

5

4

3

2

1

0

Field

TXD

RESET

X

X

X

X

X

X

X

X

R/W

W

W

W

W

W

W

W

W

Address

F40H

Note: X = Undefined.

Bit

[7:0]

TXD

Description

Transmit Data

UART transmitter data byte to be shifted out through the TXDx pin.

UART Receive Data Register

Data bytes received through the RXDx pin are stored in the UART Receive Data

(UxRXD) Register, shown in Table 68. The read-only UART Receive Data Register

shares a Register File address with the Write-only UART Transmit Data Register.

Table 68. UART Receive Data Register (U0RXD)

Bit

7

6

5

4

3

2

1

0

Field

RXD

RESET

X

X

X

X

X

X

X

X

R/W

R

R

R

R

R

R

R

R

Address

F40H

Note: X = Undefined.

Bit

[7:0]

RXD

Description

Receive Data

UART receiver data byte from the RXDx pin.

UART Address Compare Register

The UART Address Compare (UxADDR) Register stores the multi-node network address

of the UART (see Table 69). When the MPMD[1] bit of UART Control Register 0 is set,

all incoming address bytes are compared to the value stored in the Address Compare Reg-

ister. Receive interrupts and RDA assertions only occur in the event of a match.

PS022827-1212

PRELIMINARY

UART Control Register Definitions

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