CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

7.4.7 Exception Priorities

When simultaneous multiple exceptions arise, a fixed-priority system determines their order as:

1) Reset (highest priority)

2) Data abort

3) FIQ

4) IRQ

5) Prefetch abort

6) Undefined instruction, software interrupt (lowest priority)

NOTE: Not all exceptions can occur at once. Undefined instruction and software interrupt are mutually exclusive

since they each correspond to particular (non-overlapping) decodings of the current instruction.

If a data abort occurs at the same time as a FIQ and FIQs are enabled (that is, the F flag in the CPSR is

clear), the ARM processor enters the data abort handler and then immediately proceed to the FIQ vector.

A normal return from FIQ causes the data abort handler to resume execution. Placing data abort at a

higher priority than FIQ is necessary to ensure that the transfer error does not escape detection; the time

for this exception entry should be added to worst-case FIQ latency calculations.

7.4.8 Interrupt Latencies

Calculating the worst-case interrupt latency for the ARM processor is quite complex due to the cache,

MMU and write buffer and is dependent on the configuration of the whole system.

7.4.9 Reset

When the CL-PS7500FE is reset, the ARM processor abandons the executing instruction and then per-

forms idle cycles from incrementing word addresses.

When the CL-PS7500FE comes out of reset, the ARM processor does the following:

1) Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value

of the saved PC and CPSR is not defined.

2) Forces M[4:0] = 10011 (Supervisor mode) and sets the I and F bits in the CPSR.

3) Forces the PC to fetch the next instruction from address 0x00.

End of Reset Sequence

At the end of the reset sequence:

q The MMU disabled and the TLB flushed, forcing ‘flat’ translation (that is, the physical address is the virtual

address, and there is no permission checking)

q Alignment faults also disabled

q The cache disabled and flushed

q The write buffer disabled and flushed

q The ARM7 CPU core placed into 26-bit Data and Address mode, with early abort timing and Little Endian

mode

June 1997

ADVANCE DATA BOOK v2.0

61

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