CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

7.5 Configuration Control Registers

The operation and configuration of the ARM processor is controlled both directly via coprocessor instruc-

tions and indirectly through the Memory Management Page tables.

The coprocessor instructions manipulate a number of on-chip registers that control the configuration of

the Cache, write buffer, MMU, and several other configuration options.

7.5.1 Backward Compatibility

To ensure backward compatibility of future CPUs:

q Program all reserved or unused bits in registers and coprocessor instructions to ‘0’.

q Invalid registers must not be read/written.

q Program the following bits to ‘0’:

— register 1, bits 31:11

— register 2, bits 13:0

— register 5, bits 31:0

— register 6, bits 11:0

— register 7, bits 31:0

NOTE: Program the areas marked ‘reserved’ in the register and translation diagrams to ‘0’ for future compatibility.

7.5.2 Internal Coprocessor Instructions

The on-chip registers can be read using MRC instructions and written using MCR instructions. These

operations are only allowed in non-user modes and the undefined instruction trap is taken if accesses are

attempted in user mode. Refer to the CL-PS7500FE Programmer’s Guide.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Cond 1 1 1 0

n CRn

Rd

1111

1

ARM condition codes

ARM register

ARM register

1 = MRC register read

0 = MCR register write

Figure 7-5. Format of Internal Coprocessor Instructions MRC and MCR

62

REGISTER DESCRIPTIONS

ADVANCE DATA BOOK v2.0

June 1997

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