CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

When using a 16-bit-wide ROM device, data must be stored so that the least-significant bytes of a 32-bit

word are stored at the lower memory address:

Contents

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 00 0 0

Address

0x00000000

1111111111111111

0x00000001

When this is read, the ARM sees:

MSB

LSB

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1111111111111111 0000000000000000

9.1.1 ROM Bank Configuration and Timing

There are two identical registers that control the configuration and timing of the two ROM banks. Both

registers default to read-only 16-bit mode and the slowest possible non-sequential timings on reset. This

means that one of the first actions when using 32-bit-wide ROM must be to reprogram these registers for

32-bit-wide operation. A detailed description of how to boot up a CL-PS7500FE system using 32-bit-wide

ROM is contained in Appendix A, “Initialization and Boot Sequence”.

76543210

WS H B B N N N

To program these registers, write a byte to 0x03200080 for the ROMCR0 register (address range

0x00000000 to 0x00FFFFFF) or to 0x03200084 for the ROMCR1 register (address range 0x01000000 to

0x0FFFFFFF). The details of these registers are shown below.

N

B

H

S

W

Write

non-sequential access time (H = 1):

000 7 MEMCLK cycles

001 6 MEMCLK cycles

010 5 MEMCLK cycles

011 4 MEMCLK cycles

100 3 MEMCLK cycles

101 2 MEMCLK cycles

burst mode access time (H = 1):

00 Burst Off

01 4 MEMCLK cycles

10 3 MEMCLK cycles

11 2 MEMCLK cycles

half-speed select, that is, double the above cycle time when H=0

16/32-bit mode

Write enable

bit[7]

0

writes disabled

1

writes enabled

68

MEMORY SUBSYSTEMS

ADVANCE DATA BOOK v2.0

June 1997

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