CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

9. MEMORY SUBSYSTEMS

9.1 ROM Interface

The CL-PS7500FE ROM interface supports both non sequential and burst mode read and write cycles,

with a range of programmable timings for each type. A single chip select signal, nROMCS, is generated

for addresses between 0x00000000 and 0x01FFFFFF that can be split externally to provide separate chip

selects for two 16-Mbyte banks of ROM. Each bank of ROM can be 16- or 32-bits wide. The ROM access

time depends on the MEMCLK frequency and to enable slow ROMs to be used with a high-frequency

MEMCLK, there is a half-speed bit available that causes all ROM timings to slow to twice as many MEM-

CLK cycles, when the half-speed bit is set to ‘0’.

The ROM interface of CL-PS7500FE can also support write cycles with the generation of an output and

write enable. The feature is disabled on reset so that write cycles do not:

q produce a chip select – nROMCS,

q write enable, or

q drive the data out onto the external data bus

When this feature is disabled, an output enable is still generated on read cycles.

The ability to write data to ROM space devices is primarily intended to allow the programming of FLASH

devices directly. With only one write enable, byte writes to 16- or 32-bit-wide devices are not handled

directly. External logic can decode address bits LA[1:0], and the write enable can enable a full SRAM

interface to be generated (if required). However, the interface is not designed to provide a high-perfor-

mance interface to SRAM.

Assuming a MEMCLK frequency of 32 MHz, the access time for a non-sequential cycle can be varied from

220 to 62.5 ns in 31.25-ns increments. For burst mode cycles, the two LSBs of the latched address from

the CL-PS7500FE increment to allow up to four sequential reads. The access time for burst mode cycles

can be programmed from 125 ns down to 62.5 ns, again in 31.25-ns increments.

NOTE: Due to the timing of the write enable, the smallest cycle length for a write cycle is three MEMCLK cycles –

that is, 93.75 ns.

If a frequency other than 32 MHz is used for MEMCLK, these timings scale accordingly.

Support for 16-bit-wide ROMs is provided through a programmable bit in each of the ROM control regis-

ters. If a 16-bit-wide device is selected, then two memory system cycles are required to fetch the full 32-

bit word required by the ARM. If burst mode is disabled for that bank, then CL-PS7500FE performs two

non-sequential fetches using the programmed non-sequential timing, latch the intermediate 16-bit value,

and present the full 32-bit word to the ARM processor macrocell.

If the burst mode timing bits are programmed into an enabled state, then the first 16-bit read is a standard

non-sequential cycle, but the second is a burst mode cycle to minimize the total access time.

When a 16-bit-wide ROM bank is being addressed, the ROM address is shifted up by one bit such that

the LSB appears on LA[2], thus allowing the same PCB layout to be used for 16-bit or 32-bit ROM banks.

June 1997

ADVANCE DATA BOOK v2.0

67

MEMORY SUBSYSTEMS

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