CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

7.10 Register 5: Fault Status/Translation Lookaside Buffer Flush

MSB 31

12 11 10 9 8 7

43

0 LSB

0000

Domain

Status

Read: Fault Status

A read of this register returns the status of the last data fault.

It is not updated for a prefetch fault. (See Section 6 on

page 38 for more details.)

Note that only the bottom 12 bits are returned. The upper 20

bits are the last value on the internal data bus, and therefore

have no meaning. Bits 11:8 are always returned as zero.

Write: Translation Look-aside Buffer Flush A write to this register flushes the TLB. The data written is

discarded.

7.11 Register 6: Fault Address/TLB Purge

MSB 31

Fault address

0 LSB

Read: Fault Address

A read of this register returns the virtual address of the last data fault.

MSB 31

Purge address

14 13

0 LSB

Write: TLB Purge

A write of this register purges the TLB; the data is treated as an address,

and the TLB is searched for a corresponding page table descriptor. If a

match is found, the corresponding entry is marked as invalid. This allows

the page table descriptors in main memory to be updated and invalid

entries in the on-chip TLB to be purged without requiring the entire TLB to

be flushed.

7.12 Register 7: IDC Flush (Write only)

This register is write only. Data written to this register is discarded and the IDC is flushed.

7.13 Registers 8–15: Reserved

An access of any of these registers causes the undefined instruction trap to be taken.

June 1997

ADVANCE DATA BOOK v2.0

65

REGISTER DESCRIPTIONS

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