CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

7.6 Register 1: Control (Write only)

MSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R S B 1 D PWC AM

This register is write-only and contains control bits. All bits in this register are forced low at reset.

M Bit 0

A Bit 1

C Bit 2

W Bit 3

P Bit 4

D Bit 5

B Bit 7

S Bit 8

R Bit 9

ENABLE/DISABLE: When this bit is ‘0’, the on-chip MMU is turned off. When this

bit is ‘1’, the on-chip MMU is turned on.

ADDRESS FAULT ENABLE/DISABLE: When this bit is ‘0’, the alignment fault is

disabled. When this bit is ‘1’, the alignment fault is enabled.

CACHE ENABLE/DISABLE: When this bit is ‘0’, the instruction/data cache is

turned off. When this bit is ‘1’, the instruction/data cache is turned on

WRITE BUFFER ENABLE/DISABLE: When this bit is ‘0’, the WB is turned off.

When this bit is ‘1’, the WB is turned on.

ARM 32/26-BIT PROGRAM SPACE: When this bit is ‘0’, the 26-bit program space

is selected. When this bit is ‘1’, the 32-bit program space is selected.

ARM 32/26-BIT DATA SPACE: When this bit is ‘0’, the 26-bit data space is

selected. When this bit is ‘1’, the 32-bit data space is selected.

BIG/LITTLE ENDIAN: When this bit is ‘0’, the CL-PS7500FE is in little-endian oper-

ation. When this bit is ‘1’, the CL-PS7500FE is in big-endian operation.

This system bit controls the ARM processor permission system.

This ROM bit controls the ARM processor permission system.

7.7 Register 2: Level One Page Table (Write only)

This register is write only and holds the base of the currently active Level One page table.

7.8 Register 3: Domain Access Control (Write only)

MSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

This register is write only and holds the current access control for domains 0–15. See Section 6.9 on

page 48 for the access permission definitions and other details.

7.9 Register 4: Reserved

This register is reserved. Access of this register has no effect and should never be attempted.

64

REGISTER DESCRIPTIONS

ADVANCE DATA BOOK v2.0

June 1997

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