ATMEGA323L-4AI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA323L-4AI Datasheet PDF : 247 Pages
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Data Modes
ATmega323(L)
once the SS pin is driven high. If the SS pin is driven high during a transmission, the SPI
will stop sending and receiving immediately and both data received and data sent must
be considered as lost.
There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 43 and Figure 44.
Figure 43. SPI Transfer Format with CPHA = 0 and DORD = 0(1)
Note: 1. * Not defined but normally MSB of character just received.
Figure 44. SPI Transfer Format with CPHA = 1 and DORD = 0(1)
Note: 1. * Not defined but normally LSB of previously transmitted character.
SPI Control Register – SPCR
Bit
$0D ($2D)
Read/Write
Initial Value
7
SPIE
R/W
0
6
SPE
R/W
0
5
DORD
R/W
0
4
MSTR
R/W
0
3
CPOL
R/W
0
2
CPHA
R/W
0
1
SPR1
R/W
0
0
SPR0
R/W
0
SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the if the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI
operations.
71
1457G–AVR–09/03
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