ATMEGA323L-4AI View Datasheet(PDF) - Atmel Corporation
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Description
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ATMEGA323L-4AI Datasheet PDF : 247 Pages
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Clock Generation
The Clock Generation Logic generates the base clock for the Transmitter and Receiver.
The USART supports four modes of clock operation: Normal asynchronous, Double
Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL
bit in USART Control and Status Register C (UCSRC) selects between asynchronous
and synchronous operation. Double Speed (asynchronous mode only) is controlled by
the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1),
the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock
source is internal (Master mode) or external (Slave mode). The XCK pin is only active
when using synchronous mode.
Figure 46 shows a block diagram of the clock generation logic.
Figure 46. Clock Generation Logic, Block Diagram
UBRR
fosc
Prescaling
Down-Counter
UBRR+1
/2
/4
OSC
XCK
Pin
xcki
xcko
Sync
Register
Edge
Detector
U2X
/2
0
1
0
txclk
1
DDR_XCK
0
UMSEL
1
DDR_XCK
UCPOL
1
rxclk
0
Internal Clock Generation –
The Baud Rate Generator
Signal description:
txclk Transmitter clock. (Internal Signal)
rxclk Receiver base clock. (Internal Signal)
xcki Input from XCK pin (internal Signal). Used for Synchronous Slave operation.
xcko Clock output to XCK pin (Internal Signal). Used for
synchronous Master operation.
fosc XTAL pin frequency (System Clock).
Internal clock generation is used for the asynchronous and the synchronous Master
modes of operation. The description in this section refers to Figure 46.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function
as a programmable prescaler or baud rate generator. The down-counter, running at sys-
tem clock (fosc), is loaded with the UBRR value each time the counter has counted
down to zero or when the UBRRL Register is written. A clock is generated each time the
counter reaches zero. This clock is the baud rate generator clock output
(= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2,
8, or 16 depending on mode. The baud rate generator output is used directly by the
Receiver’s clock and data recovery units. However, the recovery units use a state
machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL,
U2X and DDR_XCK bits.
76 ATmega323(L)
1457G–AVR–09/03
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