ATMEGA323L-4AI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
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ATMEGA323L-4AI Datasheet PDF : 247 Pages
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ATmega323(L)
ATmega323 USART Pin
Specification
About Code Examples
AVR USART vs. AVR
UART – Compatibility
XCK (transfer clock) pin is only used by synchronous transfer mode. The Transmitter
consists of a single write buffer, a serial Shift Register, Parity Generator and control
logic for handling different serial frame formats. The write buffer allows a continuous
transfer of data without any delay between frames. The Receiver is the most complex
part of the USART module due to its clock and data recovery units. The recovery units
are used for asynchronous data reception. In addition to the recovery units, the Receiver
includes a parity checker, control logic, a Shift Register and a two level receive buffer
(UDR). The Receiver supports the same frame formats as the Transmitter, and can
detect Frame Error, Data OverRun and Parity Errors.
Table 28 shows the ATmega323 specific USART pin placement.
Table 28. ATmega323 Specific USART Pin Placement
USART Pin Name
Corresponding ATmega323 Pin
RxD
PD0
TxD
PD1
XCK
PB0
As XCK is placed on PB0, DDR_XCK in the following refers to DDB0.
This USART documentation contains simple code examples that briefly show how to
use the USART. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C compiler vendors include bit defini-
tions in the header files, and that interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation.
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers
• Baud Rate Generation
• Transmitter Operation
• Transmit Buffer Functionality
• Receiver Operation
However, the receive buffering has two improvements that will affect the compatibility in
some special cases:
• A second Buffer Register has been added. The two Buffer Registers operates as a
circular FIFO buffer. Therefore the UDR must only be read once for each incoming
data. More important is the fact that the Error Flags (FE and DOR) and the ninth
data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status
bits must always be read before the UDR Register is read. Otherwise the error
status will be lost since the buffer state is lost.
• The Receiver Shift Register can now act as a third buffer level. This is done by
allowing the received data to remain in the Serial Shift Register (see Figure 45) if the
Buffer Registers are full, until a new start bit is detected. The USART is therefore
more resistant to Data OverRun (DOR) error conditions.
The following control bits have changed name, but have same functionality and register
location:
• CHR9 is changed to UCSZ2
• OR is changed to DOR
75
1457G–AVR–09/03
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