ATMEGA323L-4AI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA323L-4AI Datasheet PDF : 247 Pages
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USART
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a highly flexible serial communication device. The main features are:
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
A simplified block diagram of the USART Transmitter is shown in Figure 45. CPU acces-
sible I/O Registers and I/O pins are shown in bold.
Figure 45. USART Block Diagram
UBRR[H:L]
BAUD RATE GENERATOR
UDR (Transmit)
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
UDR (Receive)
Clock Generator
OSC
SYNC LOGIC
PARITY
GENERATOR
CLOCK
RECOVERY
DATA
RECOVERY
PARITY
CHECKER
PIN
CONTROL
XCK
Transmitter
TX
CONTROL
PIN
CONTROL
TxD
Receiver
RX
CONTROL
PIN
CONTROL
RxD
UCSRA
UCSRB
UCSRC
The dashed boxes in the block diagram separates the three main parts of the USART
(listed from the top): Clock Generation, Transmitter and Receiver. Control Registers are
shared by all units. The clock generation logic consists of synchronization logic for exter-
nal clock input used by Synchronous Slave operation, and the baud rate generator. The
74 ATmega323(L)
1457G–AVR–09/03
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