ATMEGA323L-4AI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA323L-4AI

8-bit Microcontroller with 32K Bytes of In-System Programmable Flash

Atmel Corporation 

Frame Formats

Figure 47. Synchronous Mode XCK Timing

UCPOL = 0 XCK

RxD / TxD

UCPOL = 1 XCK

Sample

RxD / TxD

Sample

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and

which is used for data change. As Figure 47 shows, when UCPOL is zero the data will

be changed at falling XCK edge and sampled at rising XCK edge. If UCPOL is set, the

data will be changed at rising XCK edge and sampled at falling XCK edge.

A serial frame is defined to be one character of data bits with synchronization bits (start

and stop bits), and optionally a parity bit for error checking. The USART accept all 30

combinations of the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even, or odd parity bit

• 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next

data bits, up to a total of nine, are succeeding, ending with the most significant bit. If

enabled, the parity bit is inserted after the data bits, before the stop bits. When a com-

plete frame is transmitted, it can be directly followed by a new frame, or the

communication line can be set to a idle (high) state. Figure 48 illustrates the possible

combinations of the frame formats. Bits inside brackets are optional.

Figure 48. Frame Formats

FRAME

(IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE)

St

(n)

P

Sp

IDLE

Start bit, always low.

Data bits (0 to 8).

Parity bit. Can be odd or even.

Stop bit, always high.

No transfers on the communication line (RxD or TxD).

An IDLE line must be high.

78 ATmega323(L)

1457G–AVR–09/03

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