CS485NI-XYZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS485NI-XYZR Datasheet PDF : 26 Pages
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CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
5.8 Switching Characteristics — Internal Clock
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
Internal DCLK period1
Fdclk
-
CS4852x-CQZ
Fxtal
CS4854x-CQZ
Fxtal
CS4856x-CQZ
Fxtal
CS4854x-DQZ
Fxtal
CS4856x-DQZ
Fxtal
DCLKP
-
MHz
150
150
150
150
150
ns
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
T CS4854x-DQZ
CS4856x-DQZ
6.7
1/Fxtal
6.7
1/Fxtal
6.7
1/Fxtal
6.7
1/Fxtal
6.7
1/Fxtal
F 1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains locked until
the next power-on reset.
A 5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode.
R Parameter
D SCP_CLK frequency1
Symbol Min
fspisck
-
Typical
Max
Units
25
MHz
SCP_CS# falling to SCP_CLK rising
tspicss
24
-
SCP_CLK low time
tspickl
20
-
L I SCP_CLK high time
tspickh
20
-
Setup time SCP_MOSI input
tspidsu
5
-
IA H Hold time SCP_MOSI input
tspidh
5
-
SCP_CLK low to SCP_MISO output valid
tspidov
-
11
T P SCP_CLK falling to SCP_IRQ# rising
tspiirqh
-
20
N L SCP_CS# rising to SCP_IRQ# falling
tspiirql
0
SCP_CLK low to SCP_CS# rising
tspicsh
24
-
E E SCP_CS# rising to SCP_MISO output high-Z tspicsdz
-
20
SCP_CLK rising to SCP_BSY# falling
tspicbsyl
-
3*DCLKP+20
ID D 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin
CONF should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS734F2
©Copyright 2008 Cirrus Logic, Inc.
13
CONFIDENTIAL
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