CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
tiicckcmd
SCP_CLK
tiicstscl
SCP_SDA
tiicckl
tiicr
01
6
7
tiicf
8
01
tiicckcmd
6
7
8
tiicckh
tiicdov
fiicck
A6
A0 R/W ACK MSB
tiicstp
tiicbf
LSB ACK
tiicsu
tiich
T Figure 6. Serial Control Port - I2C Master Mode Timing
F 5.13 Switching Characteristics — Digital Audio Slave Input Port
A DAI_SCLK period
DAI_SCLK duty cycle
R Setup time DAI_DATAn
D Hold time DAI_DATAn
Parameter
Symbol Min
Tdaiclkp
40
-
45
tdaidsu
10
tdaidh
5
Max
-
55
-
-
Unit
ns
%
ns
ns
L I DAI_SCLK
IA H tdaidsu
T P DAI_DATAn
tdaidh
EN EL Figure 7. Digital Audio Input (DAI) Port Timing Diagram
ID D 5.14 Switching Characteristics — DSD Slave Input Port
FParameter
Symbol
DSD_SCLK Pulse Width Low
N DSD_SCLK Pulse Width High
DSD_SCLK Frequency
(64x Oversampled)
tsclkl
tsclkh
-
O DSD_A / _B valid to DSD_SCLK rising setup time
C DSD_SCLK rising to DSD_A or DSD_B hold time
tsdlrs
tsdh
Min
78
78
1.024
20
20
Typ Max Unit
-
-
ns
-
-
ns
-
3.2
MHz
-
-
ns
-
-
ns
DS734F2
©Copyright 2008 Cirrus Logic, Inc.
17
CONFIDENTIAL