CS485NI-XYZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS485NI-XYZR Datasheet PDF : 26 Pages
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CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
T Figure 8. Direct Stream Digital - Serial Audio Input Timing
AF 5.15 Switching Characteristics — Digital Audio Output Port
R Parameter
Symbol
Min
Max
Unit
DAO_MCLK period
D DAO_MCLK duty cycle
DAO_SCLK period for Master or Slave mode1
L I DAO_SCLK duty cycle for Master or Slave mode1
Master Mode (Output A1 Mode)1,2
Tdaomclk
40
-
45
Tdaosclk
40
-
40
-
ns
55
%
-
ns
60
%
IA H DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
tdaomsck
-
T P DAO_LRCLK delay from DAO_SCLK transition, respectively3
tdaomstlr
-
N L DAO_SCLK delay from DAO_LRCLK transition, respectively3
tdaomlrts
-
DAO1_DATA[3..0], DAO2_DATA[1..0]
E E delay from DAO_SCLK transition3
tdaomdv
-
Slave Mode (Output A0 Mode)4
19
ns
8
ns
8
ns
10
ns
ID D DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
tdaosdv
-
DAO_LRCLK delay from DAO_SCLK transition, respectively3
tdaosstlr
-
F DAO_SCLK delay from DAO_LRCLK transition, respectively3
tdaoslrts
-
15
ns
30
ns
15
ns
1. Master mode timing specifications are characterized, not production tested.
N 2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
DAO_SCLK, DAO_LRCLK.
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the
O data is valid.
C 4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
18
©Copyright 2008 Cirrus Logic, Inc.
DS734F2
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