CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
DAO_MCLK
DAO_SCLK
tdaomdv
tdaomlclk
tdaomsck
DAO_MCLK
DAO_SCLK
tdaomclk
tdaomsck
DAOn_DATAn
T DAO_LRCLK
tdaomlrts
DAOn_DATAn
DAO_LRCLK
tdaomstlr
AF Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
DR Figure 9. Digital Audio Output Port Timing, Master Mode
L I DAO_LRCLK
IA H DAO_SCLK
NT LP DAOn_DATAn
tdaosstlr
DAO_LRCLK
tdaosclk
DAO_SCLK
tdaosclk
tdaoslrts
E E Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
CONFID D Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
tdaosdv
DS734F2
©Copyright 2008 Cirrus Logic, Inc.
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CONFIDENTIAL