CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
SCP_CLK
tiicstscl
01
6
7
8
01
6
tiicckh
tiicdov
fiicck
7
8
tiicstp
tiicbft
SCP_SDA
A6
A0 R/W ACK MSB
LSB ACK
SCP_IRQ#
FT SCP_BSY#
tiicsu
tiich
tiicirqh
tiicirql
tiiccbsyl
A Figure 5. Serial Control Port - I2C Slave Mode Timing
DR 5.12 Switching Characteristics — Serial Control Port - I2C Master Mode
Parameter
L I SCP_CLK frequency1
IA SCP_CLK low time
H SCP_CLK high time
T P SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
Symbol
fiicck
tiicckl
tiicckh
tiicckcmd
Min
-
1.25
1.25
1.25
Max
400
-
-
N L START condition to SCP_CLK falling
tiicstscl
1.25
-
SCP_CLK falling to STOP condition
tiicstp
2.5
-
E E Bus free time between STOP and START conditions
tiicbft
3
-
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
ID D Hold time SCP_SDA input after SCP_CLK falling
tiich
20
-
SCP_CLK low to SCP_SDA out valid
tiicdov
-
18
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
CONF maximum speed of the communication port may be limited by the firmware application.
Units
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
16
©Copyright 2008 Cirrus Logic, Inc.
DS734F2
CONFIDENTIAL