CS485NI-XYZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS485NI-XYZR Datasheet PDF : 26 Pages
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CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
tspicss
tspicsx
EE_CS#
tspicsl
tspickl
0
1
2
6
7
0
5
6
7
tspicsh
SCP_CLK
fspisck
tspickh
SCP_MISO
FT SCP_MOSI
A6
tspidsu
A5
tspidh
A0 R/W MSB
tspidov
MSB
LSB
LSB
tspidz
RA Figure 4. Serial Control Port - SPI Master Mode Timing
D 5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode
Parameter
L I SCP_CLK frequency1
SCP_CLK low time
IA H SCP_CLK high time
SCP_SCK rising to SCP_SDA rising or falling for
T P START or STOP condition
Symbol
fiicck
tiicckl
tiicckh
tiicckcmd
Min
-
1.25
1.25
1.25
Typical
Max
Units
400
kHz
-
µs
-
µs
µs
N L START condition to SCP_CLK falling
tiicstscl 1.25
-
µs
SCP_CLK falling to STOP condition
tiicstp
2.5
-
µs
E E Bus free time between STOP and START conditions tiicbft
3
-
µs
Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100
ns
ID D Hold time SCP_SDA input after SCP_CLK falling
tiich
20
-
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
-
18
ns
SCP_CLK falling to SCP_IRQ# rising
tiicirqh
-
3*DCLKP + 40 ns
F NAK condition to SCP_IRQ# low
tiicirql
3*DCLKP + 20
ns
SCP_CLK rising to SCB_BSY# low
tiicbsyl
- 3*DCLKP + 20
ns
N 1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin
CO should be implemented to prevent overflow of the input data buffer.
DS734F2
©Copyright 2008 Cirrus Logic, Inc.
15
CONFIDENTIAL
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