FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
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FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
BIT 7 MOTOR ENABLE 3
This bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active.
Table 6.2 - Drive Activation Values
DRIVE
0
1
2
3
DOR VALUE
1CH
2DH
4EH
8FH
6.1.4 Tape Drive Register (TDR)
Address 3F3 READ/WRITE
The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign
tape support to a particular drive during initialization. Any future references to that drive automatically
invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 6.3
illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape
support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is
unaffected by a software reset.
Table 6.3 - Tape Select Bits
TAPE SEL1
(TDR.1)
0
0
1
1
TAPE SEL0
(TDR.0)
0
1
0
1
DRIVE
SELECTED
None
1
2
3
Table 6.4 - Internal 2 Drive Decode - Normal
DIGITAL OUTPUT REGISTER
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0
X
X
X
1
0
0
X
X
1
X
0
1
X
1
X
X
1
0
1
X
X
X
1
1
0
0
0
0
X
X
DRIVE SELECT OUTPUTS
(ACTIVE LOW)
nDS1
nDS0
1
0
0
1
1
1
1
1
1
1
MOTOR ON OUTPUTS
(ACTIVE LOW)
nMTR1
nMTR0
nBIT 5
nBIT 4
nBIT 5
nBIT 4
nBIT 5
nBIT 4
nBIT 5
nBIT 4
nBIT 5
nBIT 4
SMSC FDC37C672
Page 24
DATASHEET
Rev. 10-29-03
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