FDC37C672 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C672

Enhanced Super I/O Controller with Fast IR

SMSC -> Microchip 

Enhanced Super I/O Controller with Fast IR

Datasheet

DMA latency without causing a disk error. Table 6.14 gives several examples of the delays with aFIFO.

The data is based upon the following formula:

Threshold # x

1

x 8 - 1.5 µs = DELAY

DATA RATE

At the start of a command, the FIFO action is always disabled and command parameters must be sent

based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is

cleared of any data to ensure that invalid data is not transferred.

An overrun or underrun will terminate the current command and the transfer of data. Disk writes will

complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove

the remaining data so that the result phase may be entered.

Table 6.14 - FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT

2 Mbps* DATA RATE

1 x 4 µs - 1.5 µs = 2.5 µs

2 x 4 µs - 1.5 µs = 6.5 µs

8 x 4 µs - 1.5 µs = 30.5 µs

15 x 4 µs - 1.5 µs = 58.5 µs

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT

1 Mbps DATA RATE

1 x 8 µs - 1.5 µs = 6.5 µs

2 x 8 µs - 1.5 µs = 14.5 µs

8 x 8 µs - 1.5 µs = 62.5 µs

15 x 8 µs - 1.5 µs = 118.5 µs

Note:

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 x 16 µs - 1.5 µs = 14.5 µs

2 x 16 µs - 1.5 µs = 30.5 µs

8 x 16 µs - 1.5 µs = 126.5 µs

15 x 16 µs - 1.5 µs = 238.5 µs

*The 2 Mbps data rate is only available if VCC = 5V.

SMSC FDC37C672

Page 30

DATASHEET

Rev. 10-29-03

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