FDC37C672 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C672

Enhanced Super I/O Controller with Fast IR

SMSC -> Microchip 

Enhanced Super I/O Controller with Fast IR

Datasheet

BIT 0 and 1 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to

the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250

Kbps after a hardware reset.

BIT 2 through 4 PRECOMPENSATION SELECT

These three bits select the value of write precompensation that will be applied to the WDATA output

signal. Table 6.9 shows the precompensation values for the combination of these bits settings. Track 0 is

the default starting track number to start precompensation. this starting track number can be changed by

the configure command.

BIT 5 UNDEFINED

Should be written as a logic "0".

BIT 6 LOW POWER

A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy

controller clock and data mode after a software reset or access to the Data Register or Main Status

Register.

BIT 7 SOFTWARE RESET

This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self

clearing.

Note:

The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator

circuits will be turned off. The controller will come out of manual low power

Note:

Table 6.9 - Precompensation Delays

PRECOMP

432

111

001

010

011

100

101

110

000

PRECOMPENSATION

DELAY (NSEC)

<2MBPS

2MBPS*

0.00

0

41.67

20.8

83.34

41.7

125.00

62.5

166.67

83.3

208.33

104.2

250.00

125

Default

Default

Default: See Table 6.11

*2Mbps data rate is only available if VCC = 5V.

SMSC FDC37C672

Page 27

PRELIMINARY DATASHEET

Rev. 10-29-03

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