FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
Table 6.6 - Media ID1
INPUT
Pin 19
0
1
MEDIA ID1
BIT 7
L0-CRF1-B5 L0-CRF1-B5
=0
=1
0
1
1
0
Table 6.7 - Media ID0
INPUT
Pin 20
0
1
MEDIA ID0
BIT 6
CRF1-B4
CRF1-B4
=0
=1
0
1
1
0
Note:
Table 6.8 - Drive Type ID
DIGITAL OUTPUT REGISTER
Bit 1
Bit 0
0
0
0
1
1
0
1
1
REGISTER 3F3 - DRIVE TYPE ID
Bit 5
Bit 4
L0-CRF2 - B1
L0-CRF2 - B0
L0-CRF2 - B3
L0-CRF2 - B2
L0-CRF2 - B5
L0-CRF2 - B4
L0-CRF2 - B7
L0-CRF2 - B6
L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.
6.1.5 Data Rate Select Register (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program the data rate, amount of write precompensation, power
down status, and software reset. The data rate is programmed using the Configuration Control Register
(CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications. Other applications can
set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the
DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which
corresponds to the default precompensation setting and 250 Kbps.
7
6
5
4
3
2
1
0
S/W POWER 0
PRE- PRE- PRE- DRATE DRATE
RESET DOWN
COMP2 COMP1 COMP0 SEL1 SEL0
RESET 0
0
0
0
0
0
1
0
COND.
SMSC FDC37C672
Page 26
DATASHEET
Rev. 10-29-03
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