M69KB096AB View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M69KB096AB

64 Mbit (4Mb x 16)/ 104MHz Clock Rate 1.8V Supply - Bare Die Burst PSRAM

STMicroelectronics 

9 DC and AC parameters

M69KB096AB

Figure 26. Burst Read Showing End-of-Row Condition AC Waveforms (No Wrap)

K

Addr.

L

tKHKH

High

tKLKH, tKHKL

tF

DON'T CARE

LB/UB

Low

E

Low

Note 2

G

Low

W

WAIT

tKHTV

DON'T CARE

tEHTZ

tEHTZ

High-Z

DQ0-DQ15

VALID

VALID

OUTPUT OUTPUT

End of Row

AI11574

1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).

2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to

1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.

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