M69KB096AB View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M69KB096AB

64 Mbit (4Mb x 16)/ 104MHz Clock Rate 1.8V Supply - Bare Die Burst PSRAM

STMicroelectronics 

M69KB096AB

9 DC and AC parameters

Figure 27. Burst Read Interrupted by Burst Read or Write AC Waveforms

1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The

WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable

latency and no refresh collision.

2. The Burst Read is interrupted during the first allowable clock cycle, i.e. after the first data is received by the microcontroller.

3. The Chip Enable signal, E, can remain Low, between burst operations, but it must not remain Low for longer than tELEH.

4. If the latency is variable, WAIT is asserted tKHTV after L is clocked Low. If the latency is fixed, WAIT is asserted tLLTV after L

falling edge.

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