PIC16(L)F1512/3
FIGURE 16-10: HARDWARE CVD SEQUENCE TIMING DIAGRAM
Pre-Charge
Time
1-127 TINST
(TPRE)
Acquisition/
Sharing Time
1-127 TINST
(TACQ)
Conversion Time
(Traditional Timing of ADC Conversion)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
External and Internal External and Internal
Channels are
Channels share
Conversion starts
charged/discharged charge
Holding capacitor CHOLD is disconnected from analog input (typically 100 ns)
If ADPRE = 0
If ADACQ = 0
Set GO/DONE bit
If ADPRE = 0
If ADACQ = 0
(Traditional Operation Start)
On the following cycle:
AADRES0H:AADRES0L is loaded,
ADIF bit is set,
GO/DONE bit is cleared
DS40001624C-page 142
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