PIC16F1513T-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1513T-I/SS

28-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

16.6.10 HARDWARE CVD DOUBLE

CONVERSION PROCEDURE

This is an example procedure for using hardware CVD

to perform a double conversion for differential CVD

measurement with active guard drive.

1. Configure Port:

• Enable pin output driver (Refer to the TRIS

register).

• Configure pin output low (Refer to the LAT

register).

• Disable weak pull-up (Refer to the WPU

register).

2. Configure the ADC module:

• Select an appropriate ADC conversion clock

for your oscillator frequency.

• Configure voltage reference.

• Select ADC input channel.

• Turn on the ADC module.

3. Configure the hardware CVD module:

• Configure charge polarity and double

conversion.

• Configure pre-charge and acquisition timer.

• Configure guard ring (optional).

• Select additional capacitance (optional).

4. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt(1)

5. Start conversion by setting the GO/DONE bit or

by enabling the Special Event Trigger in the

ADDCON2 register.

6. Wait for the ADC conversion to complete by one

of the following:

• Polling the GO/DONE bit.

• Waiting for the ADC interrupt (interrupts

enabled).

7. Read ADC result:

• Conversion 1 result in ADDRES0H and

ADDRES0L

• Conversion 2 result in ADDRES1H and

ADDRES1L

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

PIC16(L)F1512/3

EXAMPLE 16-2: HARDWARE CVD

DOUBLE CONVERSION

;This code block configures the ADC

;for polling, Vdd and Vss references, Fosc/16

;clock and AN0 input.

;

; The Hardware CVD will perform an inverted

; double conversion, Guard A and B drive are

; both enabled.

;Conversion start & polling for completion

are included.

;

BANKSEL TRISA

BCF

TRISA,0

;Set RA0 to output

BANKSEL LATA

BCF

LATA,0

;RA0 output low

BANKSEL ANSELA

BCF

ANSELA,0

;Set RA0 to digital

BANKSEL WPUA

BCF

WPUA,0

;Disable pull-up on

RA0

; Initialize ADC and Hardware CVD

BANKSEL

MOVLW

MOVWF

BANKSEL

MOVLW

MOVWF

AADCON0

B'00000001’

AADCON0

AADCON1

B'11010000'

AADCON1

;Select channel AN0

;Vdd and Vss Vref

BANKSEL

MOVLW

MOVWF

BANKSEL

MOVLW

MOVWF

BANKSEL

MOVLW

MOVWF

BANKSEL

MOVLW

MOVWF

BANKSEL

MOVLW

MOVWF

BANKSEL

BSF

BTFSC

GOTO

AADCON3

B'01000011'

AADCON3

AADPRE

.10

AADPRE

AADACQ

.10

AADACQ

AADGRD

B'11000000'

AADGRD

AADCAP

B'00000000'

AADCAP

ADCON0

ADCON0, GO

ADCON0, GO

$-1

;Double and inverted

;ADOUT disabled

;Pre-charge Timer

;Acquisition Timer

;Guard on A and B

;No additional

;Capacitor

;No, test again

;RESULTS OF CONVERIONS 1.

BANKSEL AADRES0H

;

MOVF

AADRES0H,W ;Read upper 2 bits

MOVWF

RESULT0H

;store in GPR space

MOVF

AADRES0L,W ;Read lower 8 bits

MOVWF

RESULT0L

;Store in GPR space

;RESULTS OF CONVERIONS 2.

BANKSEL AADRES1H

;

MOVF

AADRES1H,W ;Read upper 2 bits

MOVWF

RESULT1H

;store in GPR space

MOVF

AADRES1L,W ;Read lower 8 bits

MOVWF

RESULT1L

;Store in GPR space

 2012-2014 Microchip Technology Inc.

DS40001624C-page 145

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