PIC16(L)F1512/3
REGISTER 16-9: AADCON2: HARDWARE CVD CONTROL REGISTER 2
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
—
TRIGSEL<2:0>(1,2)
—
—
—
bit 7
U-0
—
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
TRIGSEL<2:0>: ADC Special Event Trigger Source Selection bits(1,2)
111 = Reserved. Auto-conversion Trigger disabled.
110 = Reserved. Auto-conversion Trigger disabled.
101 = TMR2 Match to PR2
100 = TMR1 Overflow
011 = TMR0 Overflow
010 = CCP2
001 = CCP1
000 = No Auto Conversion Trigger Selection bits
Unimplemented: Read as ‘0’
Note 1: This is a rising edge sensitive input for all sources.
2: Signal used to set the corresponding interrupt flag.
2012-2014 Microchip Technology Inc.
DS40001624C-page 149