FIGURE 16-12: DOUBLE SAMPLE CONVERSION SEQUENCE (ADDSEN = 1 AND ADIPEN = 1)
Pre-charge Acquisition
AADPRE<6:0> AADACQ<6:0>
Pre-charge Acquisition
AADPRE<6:0> AADACQ<6:0>
Conversion Clock
AADRESxL/H<9:0>
1-127 TINST 1-127 TINST
(1)
(1)
(2)
10'h000
TAD
2INST1-127 TINST 1-127 TINST
(1)
(1)
(3)
10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st
10'h000
10th 9th 8th 7th 6th 5th 4th 3rd 2nd 1st
ADGRDA
(GRDPOL = 0)
ADGRDB
TPRE
TACQ
TCONV
First result written
to AADRES0L/H
TPRE
TACQ
TCONV
Second result written
to AADRES1L/H
Internal CHOLD
Charging
(ADIPPOL = 1)
External Channel
Charging
(ADEPPOL = 0)
External Channel
Connected
To Internal CHOLD
GO/DONE
ADIF
ADSTAT<2:0>
3'b001 3'b010
3'b011
3'b101
3'b110
Note 1: When the conversion clock is ADCRC, the pre-charge and acquisition timers are clocked by ADCRC.
2: The AADRES0L/H registers are set to zero during this period.
3: The AADRES1L/H registers are set to zero during this period.
3'b111
3'b000