PIC12F635/PIC16F636/639
TABLE 15-2: PRECISION INTERNAL OSCILLATOR PARAMETERS
Param
No.
Sym
Characteristic
Freq
Tolerance
Min
Typ†
Max Units
Conditions
F10
FOSC Internal Calibrated
±1%
— 8.00 TBD MHz VDD and Temperature (TBD)
INTOSC Frequency(1)
±2%
— 8.00 TBD MHz 2.5V ≤ VDD ≤ 5.5V
HFINTOSC
0°C ≤ TA ≤ +85°C
±5%
— 8.00 TBD MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
F14 TIOSCST Oscillator Wake-up from
—
Sleep Start-up Time*
—
— TBD TBD μs VDD = 2.0V, -40°C to +85°C
— TBD TBD μs VDD = 3.0V, -40°C to +85°C
—
— TBD TBD μs VDD = 5.0V, -40°C to +85°C
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.
FIGURE 15-5:
OSC1
CLKOUT
I/O pin
(Input)
I/O pin
(Output)
CLKOUT AND I/O TIMING
Q4
Q1
10
13
14
Q2
22
23
19 18
17
15
Old Value
20, 21
Q3
11
12
16
New Value
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 163