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PIC16F636T-I/SL(2005) View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC16F636T-I/SL Datasheet PDF : 196 Pages
First Prev 161 162 163 164 165 166 167 168 169 170 Next Last
PIC12F635/PIC16F636/639
15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended)
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Supply Voltage
2.0V VDD 3.6V
Operating temperature
-40°C TAMB +85°C for industrial
-40°C TAMB +125°C for extended
LC Signal Input
Sinusoidal 300 mVPP
Carrier Frequency
125 kHz
LCCOM connected to VSS
Param
No.
Sym.
VSENSE
Characteristic
LC Input Sensitivity
VDE_Q
RFLM
SADJ
Coil de-Q’ing Voltage -
RF Limiter (RFLM) must be active
RF Limiter Turn-on Resistance
(LCX, LCY, LCZ)
Sensitivity Reduction
VIN_MOD
Minimum Modulation Depth
75% ± 12%
50% ± 12%
25% ± 12%
12% ± 12%
CTUNX LCX Tuning Capacitor
Min
Typ†
Max
Units
Conditions
VDD = 3.0V
1
3.0
6
mVPP Output enable filter disabled
AGCSIG = 0; MODMIN = 00
(50% modulation depth setting)
Input = Continuous Wave (CW)
Output = Logic level transition from low-to-
high at sensitivity level for CW input.
3
5
V VDD = 3.0V, Force IIN = 5 μA
700
Ohm VDD = 2.0V, VIN = 8 VDC
0
-30
63
75
87
38
50
62
13
25
37
0
12
24
0
VDD = 3.0V
dB No sensitivity reduction selected
dB Max reduction selected
Monotonic increment in attenuation value from
setting = 0000 to 1111 by design
VDD = 3.0V
%
%
%
%
VDD = 3.0V,
pF Config. Reg. 1, bits <6:1> Setting = 000000
CTUNY LCY Tuning Capacitor
44.1
63
81.9
pF 63 pF +/- 30%
Config. Reg. 1, bits <6:1> Setting = 111111
63 steps, 1 pF/step
Monotonic increment in capacitor value from
setting = 000000 to 111111 by design
VDD = 3.0V,
0
pF Config. Reg. 2, bits <6:1> Setting = 000000
44.1
63
81.9
pF 63 pF +/- 30%
Config. Reg. 2, bits <6:1> Setting = 111111
63 steps, 1 pF/step
Monotonic increment in capacitor value from
setting = 000000 to 111111 by design
FCARRIER Carrier frequency
125
kHz Characterized at bench.
FMOD Input modulation frequency
4
kHz Input data rate, characterized at bench.
*
Note 1:
2:
Parameter is characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF
Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)
DS41232B-page 168
Preliminary
© 2005 Microchip Technology Inc.

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