FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
6.4.1
Note:
FM2112 Signals
Table 179. FM2112 XAUI Signal Pins
Signal Name
Pnn_RAN [1:24]
Pnn_RAP [1:24]
Pnn_RBN [1:8]
Pnn_RBP [1:8]
Pnn_RCN [1:8]
Pnn_RCP [1:8]
Pnn_RDN [1:8]
Pnn_RDP [1:8]
Pnn_TAN [1:24]
Pnn_TAP [1:24]
Pnn_TBN [1:8]
Pnn_TBP [1:8]
Pnn_TCN [1:8]
Pnn_TCP [1:8]
Pnn_TDN [1:8]
Pnn_TDP [1:8]
RREF [1:24]
I/O
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
Analog
Type
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Ref-erence
Description
Differential receive inputs for channel A --
Complement
Differential receive inputs for channel A -- True
Differential receive inputs for channel B --
Complement
Differential receive inputs for channel B -- True
Differential receive inputs for channel C --
Complement
Differential receive inputs for channel C -- True
Differential receive inputs for channel C --
Complement
Differential receive inputs for channel C -- True
Differential transmit outputs for channel A -
Complement
Differential transmit outputs for channel A -
True
Differential transmit outputs for channel B -
Complement
Differential transmit outputs for channel B -
True
Differential transmit outputs for channel C -
Complement
Differential transmit outputs for channel C -
True
Differential transmit outputs for channel D -
Complement
Differential transmit outputs for channel D -
True
Reference resistor pad. Connect a 1.2KΩ
resistor from each RREF pad to 1.2V VDDX or a
1Pr.0oKviΩdersesaisrteofrerfreonmceecaucrhreRnRt EfoFrtoth1e.0dVrivVeDrDaXn. d
equalization circuits.
There are twenty-four XAUI interfaces in total. The “nn” in the above signal names
represent a port number from 1 to 24.
Table 180. FM2112 High-Speed Clock Signal Pins
Signal Name
RCK1AN
RCK1AP
RCK1BN
I/O
CML (1)
LVDS
LVPECL
CML (1)
LVDS
LVPECL
CML (1)
LVDS
LVPECL
Type
Input
Input
Input
Description
Differential Reference Clock A for Ports 1, 3, 5,
7, 9, 11
Complement
Differential Reference Clock A for Ports 1, 3, 5,
7, 9, 11
True
Differential Reference Clock B for Ports 1, 3, 5,
7, 9, 11
Complement
142
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