FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
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FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
Table 181. FM2112 CPU Interface Signal Pins
Signal Name
CPU_CLK
CS_N
ADDR[23:2]
DATA[31:0]
PAR[3:0]
AS_N
RW_N
RW_INV
DTACK_N
DTACK_INV
DERR_N
I/O
Input
Input
Input
In/Out
In/Out
Input
Input
Input
Output
Input
Output
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Description
Clock for Bus Interface (maximum frequency is
100MHz)
Chip select. Active low. Enables the FM2112 to
act on an incoming request. Allows multiple
devices with the same address space to share
the bus. Two uses for the signal: (1) To enable
the start of a new request – to qualify AS_N;
(2) To qualify the outputs DATA and DTACK_N.
When asserted, the two outputs are tri-stated.
(Pull-up recommended on board.)
Address Bus. Address must be driven whenever
AS_N asserted.
Bi-directional data bus. Must be driven when
AS_N and RW_N (read) are asserted. Will be
driven on a write when DTACK_N is asserted.
The DATA bus is undriven when the device is
coming out of reset. (Pull-down recommended
on board.)
Even parity for each byte of data. PAR must be
driven when AS_N and RM_N (read) are
asserted and Ignore_Parity strapping pin is not
asserted. PAR will be driven on a write when
DTACK_N is asserted. (Pull-down
recommended on board.)
Address Strobe. Indicates the start of a valid
transaction on the bus. Active Low. Must be
inactive after reset. (Pull-up recommended on
board.)
Read/Write. Indicates when a read (active
high) or write (active low) transaction is being
requested. Determines which device drives the
data bus. Polarity can be switched through the
RW_INV strapping pin.
Inverts RW_N pin. When connected to ground,
then read is active high while write is active
low. Conversely, when connected to VDD33,
read is active low while write is active high.
Data transfer acknowledge. Indicates the
completion of a data transfer. At the
termination of a request, this signal is actively
driven inactive for 1 cycle and then tri-stated.
The pin is tri-stated when the device is coming
out of reset. Pull-up or pull-down should be
added to board, according to whether
DTACK_INV is asserted.
Strap pin. Inverts sense of DTACK_N. If
connected to ground, then DTACK_N is active
low. If connected to VDD33, then DTACK_N is
active high.
Data error occurred; transaction must be
aborted and was not completed. Indicates write
data parity errors. Only asserted (and valid)
when DTACK_N asserted. Tri-stated otherwise.
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