FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

Table 181. FM2112 CPU Interface Signal Pins (Continued)

CPU_RESET_N

INTR_N

IGNORE_PARITY

Input

Output

Input

LVTTL

SE, Open

Drain

LVTTL

Hard reset for Management block domain.

Reserved for Intel®. Connect to an external

pull-up.

Synchronous interrupt. Indicates an internal

error. The global interrupt status register must

be checked to ascertain the source of the

problem. Active Low. (Pull-up recommended on

board.)

Disables parity checking on incoming write

data.

Table 182. FM2112 DMA Pins

Signal Name

TXRDY_N

I/O

Output

Type

LVTTL

RXRDY_N

RXEOUT

Output

Output

LVTTL

LVTTL

Description

Transmit queue is ready to receive (connected to

Pause channel)

Receive queue has data to send to CPU

End of frame indication (instructs DMA controller to

begin storing data to a new frame descriptor)

Table 183. FM2112 SPI Interface Signal Pins

Signal Name

SPI_CLK

SPI_CS_N

SPI_SI

SPI_SO

I/O

Output

Output

Input

Output

Type

LVTTL

LVTTL

LVTTL

LVTTL

Description

SPI clock

SPI chip select (active low)

Serial data input

Serial data output

Table 184. FM2112 LED Interface Signal Pins

Signal Name

LED_CLK

I/O

Output

LED_DATA0

Output

LED_DATA1

Output

LED_DATA2

Output

LED_EN

Output

Type

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

Description

Provides a continuous clock synchronous to the

serial data stream output on the LED_DATA pin. Tri-

stated with LED_EN.

Serial bit stream from ports 1-8, and 0. Ports 1-8

are driven first, and then the CPU port (port 0) is

driven. Asserted on the negative edge of LED_CLK.

Tri-stated with LED_EN.

Serial bit stream from ports 9-16. Data is driven on

the negative edge of LED_CLK and is valid on the

rising edge of CLK_LED. Mode 1 inverts the polarity

of the data. Tri-stated with LED_EN.

Serial bit stream from ports 17-24. Data is driven

on the negative edge of LED_CLK and is valid on the

rising edge of CLK_LED. Mode 1 inverts the polarity

of the data. Tri-stated with LED_EN.

Used in Mode1 as the latch enable for the shift

register chain. In Mode 0, this signal is not used and

should be left unconnected. Asserted when

LED_CLK is low, coincident with the 36th bit (last bit

in LED data stream). Tri-stated with LED_EN.

145

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