FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

Note:

Table 185. FM2112 JTAG Interface Signal Pins

Signal Name

TCK

TDI

TMS

TRST_N

TDO

I/O

Input

Input

Input

Input

Output

Type

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

Description

JTAG Clock

JTAG Input Data. Internally pulled up.

JTAG Test Mode. Internally pulled up.

JTAG Reset Pin. Internally pulled up.

JTAG Data Out

When not using the JTAG interface, either drive the TCK pin with an external clock, or

drive the TRST_N pin low. Conversely, when using the JTAG interface assert TRST_N

along with chip reset to ensure proper reset of the JTAG interface prior to use.

Table 186. FM2112 Miscellaneous Signal Pins

Signal Name

CHIP_RESET_N

CONT_EN

CONT_OUT

DIODE_IN

DIODE_OUT

I/O

Input

Input

Output

Sense

Type

LVTTL

LVTTL

LVTTL

LVTTL

EEPROM_EN

AUTOBOOT

Input

Input

LVTTL

LVTTL

FH_PLL_REFCLK

FH_PLL_CLKOUT

TESTMODE

Input

Output

Input

LVTTL

Description

Hard reset for the entire chip.

SerDes continuity test enable.

SerDes continuity test output.

Die temperature is measured with a

standard temperature sensing diode.

Both terminals of the diode are

exposed through the die to the

package.

EEPROM enable. Enabled when high.

Pull low to bypass EEPROM and boot

from processor.

When asserted, the BOOT FSM starts

automatically after RESET is de-

asserted, initializing the chip

according to the content of fusebox.

Returns control to the CPU Interface

after the initialization is completed.

Pull low to boot from processor.

Refclock input to frame handler PLL

Reserved for Intel® use an should be

left unconnected.

Reserved for Intel® use. Must be

pulled down in normal operation.

146

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