FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
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FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
The scan chains are used to check the DFT state of the Intel®Ethernet
Switch Family. Access to the scan chains are granted with the following
precedence:
• External SCAN IF
• JTAG
• Management (CPU Interface or BOOT FSM)
CPU Interface
{Described in registers Table 47}
The CPU interface in the FM2112 is a 24-bit address, 32-bit data bus
used to access the registers, tables, and frames. The interface uses a
handshaking protocol to allow a variable amount of delay to respond to
requests. It supports off-chip DMA functionality.
General Description
• Slave-terminated protocol that allows a variable amount of delay to respond to
requests
• 32-bit data interface, supporting single, Big Endian, read/write transactions
• Supports parity checking on the data bus
• Interrupt generation
• Support for off-chip DMA PCI bridge devices.
• Maximum frequency range of 66MHz
• Throughput
— Reads at 528 Mb/s
— Writes at 1056 Mb/s
IO Requirements
• IO power supply = 3.3v
• VIH min = 2v, VIL max = 0.8v.
• TTL compatibility
Register Read/Write Operations
Reads and writes always act on a 32-bit word in the FM2112. Every bus
request will always return a response, even if the request was to an
unsupported address.
Table 12. CPU Interface External IO Description
Signal Name
ADDR[23:2]
RW_N
DATA[31:0]
PAR[3:0]
Direction
In
In
In / Out
In / Out
Description
Address, word aligned
Read/Write select
Data
Data parity per byte
63
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