FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5.3.4

Table 12. CPU Interface External IO Description (Continued)

AS_N

In

CS_N

In

DTACK_N

Out

DERR

Out

INTR_N

Out

CPU_RESET_N

In

Address Strobe

Chip Select

Data Acknowledge

Data Error

Interrupt

Reset

CPU Interface Operation

The CPU Interface timing diagrams are shown in Figure 17 and

Figure 18. All input signals and all output signals are driven (or tri-

stated) at the rising edge of CLK.

There are two main control signals - one to qualify the incoming

request (AS_N) and the other to qualify the completion of the request

(DTACK_N). There are no timing requirements from the start to the

completion of a request. A write will always complete its request on the

next cycle following a write request.

Figure 16. CPU Bus Interface State Diagram

64

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