FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5.6

Figure 20. Serial LED Timing Diagram

Below is the encoding of the 3 bits per port:

• Port LED0 (Red)

— Off - Port has no link synch or remote fault error

— On - Port has a link synch error or no signal

— Blinking - Port has a remote fault

• RX LED1 (Green)

— Off - Port is not enabled

— On - Port has link and is enabled

— Blinking - Port is receiving data (rate will be controllable by a programmable

decimated clock and fixed hysteresis value which when latches indicates that

traffic has been received)

• TX LED2 (Green)

— Off - Port is not transmitting data

— Blinking - Port is transmitting data (rate will be controllable by a programmable

decimated clock and some fixed hysteresis value which when latches indicates

that traffic has been transmitted.

This interface clock is a multiple of CLK_CPUI and CLK_LED.

JTAG

The JTAG controller is compliant to the IEEE 1149.1-2001 specification.

The JTAG provides basic external chip debug features,

• Access to an identification register.

• Access to the boundary scan.

• Access to the internal scan chains.

• Ability to Clamp and HighZ all outputs (except SerDes).

The maximum frequency of operation is 40MHZ.

The Supported operations of these registers are:

• Load IR (instruction register)

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