FBFM2112F897CSLJLS View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

FBFM2112F897CSLJLS

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip

Intel 

Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet

3.5.6.1

3.5.6.2

3.5.6.3

3.5.6.4

• Capture - initializes/captures/freezes value of register

• Shift - serially shifts in/out value into/out of register.

• Update - validates the contents of the register. Ie. Logic can now use the new value

for its internal operation.

The JTAG reset domain is separate and independent from the chip reset

domain.

Tap Controller

The tap controller is a finite state machine of 16 states controlled by

the 5 pin JTAG interface. It is defined by IEEE 1149.1-2001.

Instruction Register

Supported JTAG Instructions

Table 17. Supported JTAG Instructions

Instruction

IDCODE

SAMPLE/PRELOAD

EXTEST

HIGHZ

CLAMP

BYPASS

Code

(6b)

x01

x02

x03

x06

x07

x3F

Description

Selects the identification register.

Select the boundary scan register. Sample input pins to input

boundary scan register, preload the output boundary scan register.

Select the boundary scan register. Output boundary scan register

cells drive the covered output pins. Input boundary cell registers

sample the input pins.

Selects the bypass register and sets all covered output pins to high

impedance.

Forces a known value on the outputs, but uses the bypass register

to shorten scan length.

Selects the bypass register.

Bypass Register

The bypass register is a 1 bit register that connects between TDI and

TDO. When the bypass register is selected by the instruction, the data

driven on the TDI input pin is shifted out the TDO interface one cycle

later.

TAG Scan Chain

The boundary scan register is a 162-bit deep shift register. Refer to the

BSDL description file for pin assignment.

Table 18. JTAG ID Register

Bit

31:28

Silicon Version Number

Description

Value

0x00 (pre-A5)

0x01 (A5 and later)

70

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