FBFM2112F897CSLJLS View Datasheet(PDF) - Intel
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FBFM2112F897CSLJLS Datasheet PDF : 169 Pages
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Intel® FM2112 24-Port 10G/1G Ethernet Switch Chip Data Sheet
3.5.4
3.5.4.1
SPI Interface (EEPROM)
There are three supported instructions which are always aligned to 32b.
They are listed here and shown in
• WRITE(8b) - the write command will be followed by two arguments: 24b (last 2b
ignored) address and 32b data - 64b in total
• WAIT(8b) - the wait command will be followed by 1 argument: 24b cycles to wait.
Cycles are expressed in terms of the SPI clock, which is derived from the CPU clock
(See Table 40). - 32b total
• DONE (8b) - EEPROM sequence is finished. Followed by RSVD (24b).
Table 14. SPI write Sequence
0
Dummy Byte (required for 2B addressing only).
1
CMD = Write
2
ADDR (MSB)
3
ADDR
4
ADDR (LSB)
5
DATA (MSB)
6
DATA
7
DATA
8
DATA (LSB)
9
CMD = DELAY
10
SPI_CLKS (MSB)
11
SPI_CLKS
12
SPI_CLIKS (LSB)
13
FF
14
FF
15
FF
16
FF
WRITE
WAIT
DONE
SPI (Serial Peripheral Interface) Controller
A Serial peripheral Interface is needed to access bootstrap code from
an off chip ROM.
• The SPI interface has the following constraints
— Natively supports 3 byte addressing
— 2-Byte addressing may be used by shifting all data up by 1 byte
• Support of one Chip Select
— The EEPROM size is restricted to 64Kb - 2Mb - this is sufficient for about 30k
instructions in a 2Mb part.
• Support of one Mode 0 (CPOL=0,CPHA=0 - transmit data on the falling edge of the
SPICLK and receive data on the rising edge of the SPICLK signal) device (only one
CS required)
• Support frequency of operation up to 40 MHz
• Interoperability note: The SPI works with following parts:
66
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