DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Legacy Bridge—Intel® Quark SoC X1000
21.7
Legacy SPI Controller
The Legacy SPI Controller provides an interface to a SPI Flash device that contains the
SoC firmware.
21.7.1
Signal Descriptions
See Chapter 2.0, “Physical Interfaces†for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristicsâ€
• Description: A brief explanation of the signal’s function
Table 119. Legacy SPI Signals
Signal Name
LSPI_MOSI
LSPI_MISO
LSPI_SS_B
LPSI_SCK
Direction/
Type
Description
O
Legacy SPI Data Output
I
Legacy SPI Data Input
O
Legacy Chip Select Signal
O
Legacy SPI Clock Output
21.7.2
Features
The Legacy SPI Controller provides access to system firmware that resides on a SPI
Flash device connected to the 4-pin Legacy SPI interface. SPI Flash devices up to
16 MByte in size are supported. A SPI clock frequency of 20 MHz is supported.
The Legacy SPI Controller supports direct memory reads from the processor. All other
operations are controlled via the SPI Host Interface registers that reside in the RCRB
Memory Space in the range 3020h to 308Fh.
To protect the integrity of system firmware, the Legacy SPI Controller provides two
write protection mechanisms, one scheme based on address ranges and one SMI#-
based scheme. If either mechanism indicates an access should not be allowed, then
that write access is blocked.
21.7.3
Register Map
See Chapter 5.0, “Register Access Methods†for additional information.
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
841
Share Link: 