DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

DHQ1ECCSECETS1SR1WH

Intel® Quark SoC X1000

Intel 

Legacy Bridge—Intel® Quark SoC X1000

21.6

Legacy GPIO

The SoC provides a total of 16 GPIOs. Ten of these GPIOs are available for use during

the S0 ACPI state. The remaining 6 GPIOs are available for use during both the S0 and

S3 ACPI state. The GPIOs are split between the Legacy Bridge (0/31/0) and the GPIO

Controller (0/21/2). The GPIOs within the Legacy Bridge are referred to as Legacy

GPIOs and are described in this section.

21.6.1

Signal Descriptions

See Chapter 2.0, “Physical Interfaces” for additional details.

The signal description table has the following headings:

• Signal Name: The name of the signal/pin

• Direction: The buffer direction can be either input, output, or I/O (bidirectional)

• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”

• Description: A brief explanation of the signal’s function

Table 117. Legacy GPIO Signals

Signal Name

GPIO[9:8]

GPIO_SUS[5:0]

Direction/

Type

Description

I/O

Varies

I/O

Varies

These Legacy GPIO pins are powered and active in S0 only.

These Legacy GPIO pins are powered and active in S3 and S0.

21.6.2

Features

GPIOs can generate general purpose events (GPEs) on rising and/or falling edges.

The suspend well GPIOs, GPIO_SUS[5:0], can be used to generate wake events when

the system is in the ACPI S3 state.

21.6.3

Use

Each GPIO has six registers that control how it is used, or report its status:

• Use Select

• I/O Select

• GPIO Level

• Trigger Positive Edge

• Trigger Negative Edge

• Trigger Status

The Use Select register selects a GPIO pin as a GPIO, or leaves it as its programmed

function. This register must be set for all other registers to affect the GPIO.

The I/O Select register determines the direction of the GPIO.

The Trigger Positive Edge and Trigger Negative Edge registers enable general purpose

events on a rising and falling edge respectively. This only applies to GPIOs set as input.

October 2013

Document Number: 329676-001US

Intel® Quark SoC X1000

DS

831

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