DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:6
0b
RO
Reserved (RSV): Reserved.
Trigger Enable (TE): When set, the corresponding GPIO, if enabled as input via
5:0
0h
RW
RGIO.IO[n], will cause an NMI/SMI/SCI when a 0 to 1 transition occurs. When cleared,
the GPIO is not enabled to trigger an NMI/SMI/SCI on a 0 to 1 transition. This bit has no
meaning if RGIO.IO[n] is cleared (i.e. programmed for output)
21.6.5.13 Resume Well GPIO Trigger Negative Edge Enable (RGTNE)—Offset 30h
Access Method
Type: I/O Register
(Size: 32 bits)
RGTNE: [GBA] + 30h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:6
0b
RO
Reserved (RSV): Reserved.
Trigger Enable (TE): When set, the corresponding GPIO, if enabled as input via
5:0
0h
RW
RGIO.IO[n], will cause an NMI/SMI/SCI when a 1 to 0 transition occurs. When cleared,
the GPIO is not enabled to trigger an NMI/SMI/SCI on a 1 to 0 transition. This bit has no
meaning if RGIO.IO[n] is cleared (i.e. programmed for output)
21.6.5.14 Resume Well GPIO GPE Enable (RGGPE)—Offset 34h
Access Method
Type: I/O Register
(Size: 32 bits)
RGGPE: [GBA] + 34h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Intel® Quark SoC X1000
DS
838
October 2013
Document Number: 329676-001US
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