DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
| |||
Legacy Bridge—Intel® Quark SoC X1000
21.6.5.10 Resume Well GPIO Input/Output Select (RGIO)—Offset 24h
Access Method
Type: I/O Register
(Size: 32 bits)
RGIO: [GBA] + 24h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 0000003Fh
31
28
24
20
16
12
8
4
0
00000000000000000000000000111111
Bit
Default &
Range Access
Description
31:6
0b
RO
Reserved (RSV): Reserved.
5:0
3Fh
RW
Input/Output (IO): When set, the GPIO signal (if enabled) is programmed as an
input. When cleared, the GPIO signal is programmed as an output.
21.6.5.11 Resume Well GPIO Level for Input or Output (RGLVL)—Offset 28h
Access Method
Type: I/O Register
(Size: 32 bits)
RGLVL: [GBA] + 28h
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
31
28
24
20
16
12
8
4
0
00000000000000000000000000000000
Bit
Default &
Range Access
Description
31:6
0b
RO
Reserved (RSV): Reserved.
Level (LVL): If the GPIO is programmed to be an output (RGIO.IO[n] cleared), then
5:0
0h
RW
this bit is used by software to drive a value on the pin. 1 = high, 0 = low. If the GPIO is
programmed as an input, then this bit reflects the state of the input signal (1 = high, 0
= low.) and writes will have no effect. The value of this bit has no meaning if the GPIO is
disabled (RGEN.EN[n] = 0).
21.6.5.12 Resume Well GPIO Trigger Positive Edge Enable (RGTPE)—Offset 2Ch
Access Method
Type: I/O Register
(Size: 32 bits)
RGTPE: [GBA] + 2Ch
GBA Type: PCI Configuration Register (Size: 32 bits)
GBA Reference: [B:0, D:31, F:0] + 44h
Default: 00000000h
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
837
Share Link: 